HBM Taxes Commodity DRAM — It Doesn't Destroy It, and the Wafers Are Already Coming Back

A 4x Premium Against a 3x Penalty: Why the Wafers Moved, and Why They Are Moving Back

Start with the two numbers that explain the entire episode, and put them side by side.

As of 2Q25, TrendForce reports, HBM3e "still commanded a price premium more than four times that of DDR5, providing much stronger profitability for suppliers." [9] Against that premium stood a wafer penalty — the number of wafers HBM burns to make the same bits as conventional DRAM — of roughly 2.85x, which we derive below from TrendForce's own published shares and which lands squarely on the "three-to-one trade ratio with DDR5" Micron's CEO described on the FQ1-2026 earnings call. [13]

A four-times price premium against a roughly three-times wafer penalty is not a physical catastrophe. It is a profitable trade. That is why the wafers went to HBM: not because AI seized the fabs by force, but because for eighteen months a wafer pointed at HBM made more money than a wafer pointed at DDR5, and three companies that make essentially every DRAM wafer-allocation decision on earth did the obvious arithmetic.

Then the arithmetic changed. Conventional DRAM contract prices rose roughly 95% in a single quarter. [18] TrendForce had forecast the consequence in October 2025 — "since HBM3e and DDR5 compete for the same production capacity... suppliers may allocate more resources toward server DDR5 to secure earnings" [9] — and confirmed it in June 2026: "HBM wafer revenue was overtaken by DDR5 64GB RDIMM in 1Q26. This has led HBM profitability to also fall below that of DDR5 64GB RDIMM since 1Q26." [6] The trade inverted. The wafer penalty did not change; the price did.

And the wafers started coming back. DIGITIMES reports that Samsung "has shifted its internal strategy in response to intensified HBM market competition, reallocating capacity toward DDR5 RDIMM modules and freeing up around 80,000 DRAM wafers monthly to yield stronger profits." [24] (A sourcing caveat we will repeat rather than bury: only the teaser paragraph of that article is accessible; the body is paywalled. The figure is quotable, the supporting detail is not verified.) At the node level the same reversal is under way — as Samsung transitions from HBM3/HBM3E to HBM4 it "is reportedly reallocating part of its HBM output back to standard DRAM," with internal plans to convert "roughly 30–40% of Samsung's 10 nm-class, fourth-generation 1a DRAM capacity into 10 nm-class, fifth-generation 1b lines for general-purpose memory, covering DDR5, LPDDR5X, LPDDR6, and GDDR7." [11]

Micron itself states the mechanism as running in both directions, in the same risk factor that makes the wafer-intensity claim: "If demand for HBM weakens and suppliers shift capacity from HBM to conventional DRAM, this could result in a significant increase in conventional DRAM supply." [1] A supply curve that the issuer says can shift back is not a destroyed supply curve.

So here is the call. HBM's wafer penalty is real, it is asserted in tier-1 filings under disclosure liability, and it is independently reproducible from third-party data. But it taxes commodity DRAM rather than destroying it. And three parts of the popular framing do not survive the evidence: HBM does not destroy conventional supply (bits are still growing in the "low to mid-20s percentage range" [14]); this is not a pure supply-curve left-shift (quantity and price are rising together, which is the signature of demand); and the rally is not still accelerating (contract growth has decelerated from roughly 95% to 63% [18]). The mechanism survives. The framing does not.

The Mechanism Is Tier-1. The Number Is Not.

Everything downstream depends on whether HBM really does eat more silicon per bit. It does, and this is not a trade-press inference. It is asserted by two of the three companies that make the wafers, in documents that carry US securities-disclosure liability.

Micron's Form 10-Q for the quarter ended May 28, 2026 states it in a risk factor:

"Due to the higher performance and more complex manufacturing process, HBM requires a higher number of wafers and more cleanroom space to produce the same number of bits as conventional DRAM in the same technology node." [1]

SK hynix says the same thing in its own words in its SEC-registered US listing prospectus. Producers "have allocated their limited cleanroom space and capital expenditure to the production of HBM, given its robust demand and the significantly higher complexity and wafer intensity of its manufacturing process compared to traditional DRAM," and HBM "requires greater wafer input." The prospectus goes further and attributes the price recovery itself to "structural undersupply arising from the industry-wide reallocation of production capacity to HBM." [5]

Two details matter enormously here. The first is the date. The identical wafer-intensity language already appears in Micron's FY2025 Form 10-K, filed 2025-10-03 — before the price spike. [2] This is not a post-hoc rationalisation invented in 2026 to explain a shortage after the fact. It was on the record as a risk before the risk materialised.

The second is the qualifier: "in the same technology node." Micron's own formulation is narrower than the way it is usually quoted. It says nothing about a wafer of 1-gamma HBM versus a wafer of 1a DDR5. It compares like node with like node — which explicitly leaves the node-migration offset intact, and we will come back to that.

What the filings will not do is give you a number

Here is the sourcing limit, and the report states it plainly rather than smuggling past it. The phrase "trade ratio" appears in no SEC filing. Micron's 10-K and 10-Q assert the direction of the mechanism unambiguously and quantify nothing. SK hynix's prospectus quantifies nothing. [1] [2] [5]

The quantified anchor exists only in earnings-call remarks. Micron, 17 December 2025: "The dramatic increase in HBM demand is further challenging the supply environment due to the three-to-one trade ratio with DDR5, and this trade ratio only increases with future generations of HBM." [13] Note precisely what is being claimed: a ratio versus DDR5 specifically, not versus all conventional DRAM, and not explicitly per-gigabyte. Micron restated the mechanism six months later — "HBM's growth and increasing trade ratio with every new generation further pressures non-HBM supply" — alongside the observation that "wafer growth needs are significantly increasing clean room space and greenfield fab requirements" and that "supply is structurally constrained in its growth and ability to meet industry demand." [14] But it has never defined the term.

The version of the number that actually circulates comes from elsewhere. Tom's Hardware, 19 December 2025: "Each gigabyte of HBM consumes roughly three times the wafer capacity of DDR5. That reflects both yield loss from stacking and the fact that many DRAM dies in HBM stacks are smaller or binned lower than equivalent RAM sticks." [17] The article cites no analyst and no primary source. On its own it is unusable. It survives only because Micron independently said "three-to-one" two days earlier.

And there is a negative finding here worth publishing in its own right: no teardown house has ever confirmed any multiple. Searches for an independent, teardown-based wafer-per-bit ratio for HBM versus DDR5 return Tom's Hardware, SemiAnalysis, and a long tail of aggregators recirculating either the Micron quote or the Tom's Hardware headline. There is no independent physical confirmation of 3x in the public record. [17] [15]

The formulation we refuse to inherit

One arithmetic error is loose in the coverage and it would invalidate this piece if we repeated it. The claim, in Tom's Hardware's framing, is that "with wafer starts flat and packaging lines locked, every wafer pushed into HBM removes capacity from commodity DRAM and NAND," which several aggregators have upgraded into the assertion that shifting one wafer to HBM removes three wafers' worth of consumer DRAM from the pool. [17]

That is false. One wafer diverted removes one wafer. The multiple is bits-per-wafer, not wafers-per-wafer: it governs how many wafers a given quantity of HBM bit demand consumes, and nothing more. Any draft that asserts a 3x-amplified loss of conventional wafers is triple-counting its own effect size. We will not, and the interactive model below is built so that it cannot.

Don't Take the Manufacturer's Word for It — Derive the Penalty From TrendForce's Own Numbers

An earnings-call number from the company with the strongest commercial incentive to justify HBM pricing is not an anchor. It is a hypothesis. What rescues it is that the same magnitude falls out of an entirely independent dataset — one published by a firm with no stake in Micron's pricing power.

TrendForce publishes both halves of the pair you need. On wafers, an estimate: "HBM wafer input among the top three suppliers will account for approximately 18%, 22%, and 30% of total DRAM wafer input by the end of 2025, 2026, and 2027, respectively." [6] On bits, from the same release: "HBM bit supply is expected to represent approximately 8%, 9%, and 13% of total DRAM bit supply during the same period." [6] Both are TrendForce estimates, not measurements, and TrendForce says so — its per-wafer comparison is "estimated using die size, yield rates, and per-Gb pricing." [6] It is a model.

But it is a model that lets you do the arithmetic yourself. Take 2026. HBM takes 22% of the wafers and yields 9% of the bits. Conventional DRAM therefore takes the residual 78% of the wafers and yields 91% of the bits. Conventional bits per wafer-point are 91/78 = 1.167; HBM bits per wafer-point are 9/22 = 0.409. Divide one by the other and you get a wafer-per-bit penalty of 2.85x.

Run the same method on the other two years and you get 2.52x for 2025 (92/82 ÷ 8/18) and 2.87x for 2027 (87/70 ÷ 13/30).

That is the single most important arithmetic in this report, because it does not take the manufacturer on trust. An independent forecaster's published shares, ground through nothing more exotic than division, land on Micron's "three-to-one." Convergence from a separate dataset is what turns an earnings-call slogan into a defensible anchor.

The denominator trap that produces the wrong number

A warning, because sloppy versions of this calculation are circulating. If you simply divide HBM's wafer share by HBM's bit share — 22 ÷ 9 — you get 2.4x. That is the wrong comparison. It measures HBM against the DRAM industry average, and the industry average already contains HBM. It understates the penalty. The correct comparison is HBM against conventional DRAM only, which is the 2.85x above. The 2.4x figures you will find online are this mistake.

Now decompose it, and admit what nobody can source

Where does 2.85x actually come from? Only part of it can be traced to measured silicon.

SemiAnalysis provides the only direct die-level measurement in the public record: "SK Hynix D1z DDR4 has a bit density of 0.296 Gb/mm2, 85% more dense than their HBM3 which is 0.16 Gb/mm2," with the explanation that "the additional area required to fit these TSVs is what makes HBM die sizes larger than their DDR equivalent." [15] Divide the densities and the pure silicon-area penalty per bit is roughly 1.85x. It comes with a serious caveat: that is D1z DDR4 against HBM3 — an obsolete generation pair, not HBM4 against DDR5 on 1-gamma.

The second measurable channel is stacking scrap. SemiAnalysis again: "Take an 8-layer stack with 99% stack yield per layer; total yield will be 92%. For a 12-layer stack, this becomes 87%." [15] A 12-hi stack therefore throws away roughly 13% of otherwise-good silicon at the stack level, which multiplies the die-area penalty by about 1.15x.

Compose the two channels that can actually be sourced — 1.85 × (1 ÷ 0.87) — and you reach 2.13x. That is well short of the 2.85x TrendForce's shares imply, and well short of the three-to-one Micron claims.

The gap is a residual of roughly 1.34x, and here is the honest statement of the report's own weakness: that residual is explained by no named public source. It has to be absorbed by wafer-level die yield on the larger HBM die, known-good-die sort losses, burn-in and test scrap, and the logic base die. Those are all plausible. None of them is published. The correct formulation, and the one this report uses, is that the three-to-one is a measurable ~1.85x silicon penalty plus an unaudited ~1.34x yield and process penalty asserted by manufacturers and confirmed by nobody.

SemiAnalysis is the source most likely to be cited as corroboration for 3x, and it is worth saying clearly that it does not corroborate 3x. Its numbers corroborate the mechanism and undercut the magnitude. It also contains a twist that runs directly against the shortage thesis: "All manufacturers have absolute yields well below what they're accustomed to compared to their conventional memory wafers," and "for Samsung, yields are even worse. Ironically, their low yields tighten up the total DRAM wafer supply." [15] If a meaningful slice of the trade ratio is a yield artefact of immature HBM manufacturing, then maturing yields would improve the ratio and ease the squeeze.

Which is why you should never quote the multiple naked

There is a competing figure from the same publisher, and we report it rather than averaging it away. TrendForce, in December 2025, estimated that "1GB of HBM consumes 4x the capacity of standard DRAM, while GDDR7 requires 1.7x." [7] That is 4x — inconsistent with TrendForce's own June 2026 wafer and bit shares, which imply 2.85x.

The GDDR7 number in that same sentence is the useful control on the whole concept. At 1.7x for GDDR7, it is obvious that the "multiple" is a continuous function of die complexity, TSV overhead and yield — not a magic constant that attaches to the letters HBM. Any figure quoted without a generation, a node pair and a yield assumption is close to meaningless.

So: publish the range, not the slogan. Roughly 2.5x to 3x, centred on 2.85x, with a hard silicon floor at 1.85x and a published outlier at 4x. Then hand the reader the model and invite them to break it.

2026 (TrendForce shares)2027 (TrendForce shares)HBM yields mature — the ratio decaysCleanroom binds hard — no new wafersReset

HBM share of DRAM wafer input, this yearestimate22%

HBM share of DRAM bit supply, this yearestimate9%

HBM share of wafer input, prior yearestimate18%

HBM share of bit supply, prior yearestimate8%

Growth in TOTAL DRAM wafer startsassumption5%

Bits-per-wafer gain from node migrationassumption12%

Implied wafer-per-bit penalty of HBM vs conventional DRAM2.85×x

How much higher industry bit supply would be with no HBM16.7%

Percentage points of bit-supply GROWTH that HBM subtracts this year4pp

Total wafer-start growth needed just to hold conventional wafer starts FLAT5.1%

Actual growth in CONVENTIONAL wafer starts-0.1%

Resulting growth in CONVENTIONAL DRAM bit supply11.9%

Read the defaults as TrendForce's 2026 estimates. Two things this model deliberately will NOT do. (1) It never multiplies wafers by the trade ratio: one wafer diverted to HBM removes exactly ONE wafer from the conventional pool. The multiple is bits-per-wafer, not wafers-per-wafer — the widely repeated "shift one wafer, lose three" formulation triples its own effect size and is simply wrong. (2) It does not pretend the wafer-start slider is sourced. It is an assumption; we could not find a wafer-start series (kwpm) with a snapshot that survives our sourcing gate, and the whole wafer-side argument in this report rests on it. Push it above the stand-still threshold and the supply-destruction channel closes.

It Taxes Commodity DRAM. It Does Not Destroy It — and the Price Signature Says Demand

Now the two kills.

Kill one: "destroys" is arithmetically impossible

Micron's management, in June 2026: "In DRAM, we expect industry DRAM bit shipments in calendar 2026 to grow in the low to mid-20s percentage range." [14] That is a projection, made by the company. It follows a year in which, per Micron's December 2025 commentary, "bits shipped are now expected to increase by around 20 percent for both DRAM and NAND compared to 2025," after industry DRAM bit shipments in the low 20 percent range for calendar 2025. [22] [11]

And HBM is only about 9% of bits. [6]

There is no arithmetic path from those two facts to a contraction in conventional DRAM bits. Two consecutive years of roughly 20% industry bit growth, with HBM taking under a tenth of the output, is a supply curve shifting out more slowly than demand — not a supply curve in reverse. No year in the forecast horizon contains a decline in non-HBM bits, and the cleanest possible falsifier of the word "destroys" — a single quarter in which top-three combined non-HBM DRAM bit shipments fall year over year — has not occurred.

So size the real effect honestly instead. Using the same TrendForce shares: if HBM's wafers had been run as conventional DRAM at conventional bits-per-wafer, industry DRAM bit supply would be about 16.7% higher in 2026 and about 24.3% higher in 2027. Expressed as a growth drag, HBM subtracts roughly 4.0 percentage points of DRAM bit-supply growth in 2026 and roughly 6.5 percentage points in 2027.

That is a large, persistent, publishable tax. It is not a destruction. The verbs are taxes, suppresses, steepens.

What is paying the tax

The offsets covering it are visible and they are mostly node migration. Micron: "1-gamma will be the primary driver of our DRAM bit growth in calendar 2026 and will be the majority of our bit output in the second half of the calendar year." [13] SemiAnalysis estimates that "Samsung's leading-edge 1c DRAM process node delivers roughly ~70% higher bits output per wafer compared with its 1a node" — real and large, but spanning two full node steps over several years, which makes it a one-time multi-year gain rather than an annual one. [16]

And the density lever is shrinking. SemiAnalysis again, with the decisive number: "Over the past decade, DRAM density has increased by only ~2× in total, versus roughly ~100× per decade during the industry's peak scaling era." [16] A 2x decade is roughly 7% a year of bits-per-wafer improvement. DRAM scaling is, for practical purposes, dead.

Nor is there slack to absorb the tax. SemiAnalysis estimates that "utilization can swing dramatically across cycles, ranging from roughly 95% in a supercycle to as low as 50% in significant downcycles" — and the industry is at the top of that range. [16] The usual first-line offset, running idle tools harder, is unavailable.

Micron concedes the point in a tier-1 filing: "In addition to the supply capacity we generate through our proprietary product and process technology that increases bit density per wafer, we will need to add new DRAM wafer capacity to support projected memory demand in the second half of the decade and beyond." [1] The node cannot carry it forever. But in 2026 it is carrying it.

Kill two: the quantity-price signature is a demand shock

The hypothesis's framing — a supply-curve shift, not a demand spike — makes a testable prediction. A leftward shift in supply produces lower quantity at a higher price. That is what "supply destruction" means in a diagram.

Here is what Micron's 10-Q actually reports for FQ3-26: "Sales of DRAM products increased 343%, primarily due to a low-260% range increase in average selling prices and a low-20% range increase in bit shipments." [1] Over nine months, DRAM sales rose 211% on an approximate 140% increase in average selling prices and an approximate 30% increase in bit shipments. [1]

Quantity up. Price up. Both, together, hard. That is not a supply curve moving left. That is a demand curve moving right along a supply curve that has become steep and inelastic — and HBM's contribution is to the steepness, not to a leftward shift.

The producers say as much themselves. SK hynix's prospectus: "expanding data processing and storage demand from AI accelerators and data centers is driving increasing demand not only for HBM but also for traditional DRAM products such as server DDR5 and RDIMM." [5] Samsung's Memory Business "seeks to spearhead the AI memory market... by continuing to expand its share of high-value-added AI products like DDR5, SOCAMM2 and others" — both of which are conventional DRAM products, sold to AI buyers. [19] AI is not only pushing wafers away from commodity DRAM. It is also pulling commodity DRAM demand up. The clean "supply shift, not demand" framing is too tidy for its own evidence.

An independent price series — not TrendForce's, and sitting inside a tier-1 registered document — confirms the scale of the price move without settling its cause. Gartner data cited in SK hynix's prospectus projects that traditional DRAM's average selling price, having increased 45.2% year over year in 4Q25, will increase 136.4% and 198.1% year over year in 1Q26 and 2Q26 respectively. [5]

The one fact that genuinely argues supply-side — and its contamination

There is exactly one observation in this file that a demand spike cannot manufacture: rising cost per bit. Prices can be bid up by demand; costs cannot. And Micron reports that in the December quarter "the cost per bit of DRAM rose by 20 percent and bits shipped were only up slightly," [22] and now guides "the blended DRAM cost per bit to rise from current levels." [14] For four decades DRAM cost per bit fell. A rising cost curve is a supply-side structural break, and it is the strongest card the wafer-cannibalisation thesis holds.

But it is contaminated, and the contamination is load-bearing. NAND cost per bit rose in the "mid-teens" over the same period, on mid-to-high-single-digit bit growth. [22] NAND contains no HBM and competes for no DRAM wafers. TrendForce projects NAND flash contract prices rising 55–60% quarter over quarter in 1Q26 — revised upward from 33–38% — with enterprise SSD up 53–58%, "a new record for quarterly price increases." [8] Tom's Hardware reports contract pricing on NAND rose 60% in November. [17]

If NAND is also setting records, and NAND's cost per bit is also rising, then a large part of the memory shock is a general capital-underinvestment phenomenon that has nothing to do with HBM eating DRAM wafers. The monocausal story does not survive contact with the NAND data.

Where the rent lands

The scarcity rent is extraordinary and it is concentrated. Micron's FQ3-26: revenue of $41.46 billion, GAAP gross margin of 84.6% of revenue against 37.7% a year earlier, operating margin 80.4%, net income $28,243M or $24.67 per diluted share. [3] The 10-Q frames the jump as gross margin rising "to 85% for the third quarter of 2026 from 74% for the second quarter of 2026." [1] The quarterly progression — $13,643M, then $23,860M, then $41,456M — shows a price shock compounding, not a one-off. [3] [4] Guidance for FQ4-26 is revenue of $50.0 billion ± $1.0 billion at approximately 86% gross margin. [3]

SK hynix posted 52.5763 trillion won of revenue and 37.6103 trillion won of operating profit in Q1 2026 — a 72% margin, with operating profit nearly doubling from 4Q25's 19.1696 trillion won. [20] Samsung reported KRW 133.9 trillion of consolidated revenue and KRW 57.2 trillion of operating profit, of which the Device Solutions division alone contributed KRW 81.7 trillion of revenue and KRW 53.7 trillion of operating profit, attributing the record to a Memory Business that "surpassed its quarterly sales record by addressing high-value-added AI demand despite limited supply availability, with industry-wide memory price increases also a contributing factor." [19] A 72% operating margin on a commodity product is not a semiconductor margin. It is a rationing margin.

Who is rationed is named in a tier-1 filing. SK hynix: "This significant increase in demand for HBM and server DRAM has significantly constrained the supply of PC, mobile and consumer DRAM for the traditional DRAM market as semiconductor producers seek to allocate their manufacturing capacity." [5] Micron's 10-Q concedes the same, that allocation under scarcity "has led to decisions on supply allocation that may impact certain customers and end markets." [1] The crowding-out is explicitly PC, mobile and consumer — not enterprise server. And who is paying is equally visible: Micron's Cloud Memory Business Unit turned over $13,769M in FQ3-26 and Core Data Center $11,524M, against Mobile and Client at $11,521M. [3] The AI-adjacent buyers are now the largest single source of the industry's scarcity rent, paid at an 84.6% gross margin.

What this report does not do is trace the incidence downstream. We researched what happened to PC OEMs, phone makers, automakers and hyperscalers, and the answers were interesting — but not one of those filings is in this report's verified source set. Publishing figures attributed to documents we cannot show would be exactly the failure this piece exists to avoid. The incidence section is out of scope until those filings are fetched and snapshotted, and we say so rather than quietly using the numbers anyway.

Source: Micron Technology, Form 10-Q for the quarter ended May 28, 2026

In Wafer Terms the Thesis Keeps Its Teeth — But the Offset That Works on a 2026 Clock Is Not a Fab

Bits flatter the industry. Wafers indict it.

Take TrendForce's HBM wafer shares and subtract them from the whole: conventional DRAM's share of the wafer pool falls from 82% to 78% to 70% across 2025, 2026 and 2027. [6] That is a 4-point loss in 2026 and a further 8-point loss in 2027 — and it is the quantity the hypothesis actually needs, not the bit numbers.

From it comes the cleanest test in the file, and it requires no external data at all. For conventional wafer starts to hold merely flat, total DRAM wafer starts must grow by more than 5.1% in 2026 (82/78 − 1) and by more than 11.4% in 2027 (78/70 − 1). Anything less and the absolute number of wafers producing commodity DRAM shrinks, whatever the bits are doing.

Is total wafer-start growth clearing those bars? We do not know, and this is the softest joint in this report. We could not source a hard wafer-start series (in thousands of wafers per month) to a snapshot that survives our sourcing gate. The wafer-side argument is therefore asserted, not proven. We put that in the open rather than at the bottom, and the model above exposes wafer-start growth as a slider precisely so that a reader who thinks we are wrong can make it say so.

Cleanroom, not capital, is what binds

What we can establish is why the bar is hard to clear. The constraint is not money. TrendForce, in November 2025: "cleanroom capacity in the DRAM industry remains limited." [10] Micron, in June 2026: "Wafer growth needs are significantly increasing clean room space and greenfield fab requirements." [14] TrendForce adds that "only Samsung and SK hynix can modestly expand their lines, while Micron must wait for its new ID1 fab in the U.S., which isn't expected to start operations until 2027." [11]

That is why rationing, not merely tightness, is the operative word. Micron "acknowledged that it is currently able to meet only around 55%–60% of core customer demand, while warning that the memory supply crunch is likely to persist beyond 2026," [11] and told the same call: "In the medium term, we are only able to meet about 50% to two-thirds of our demand from several key customers." [13] Three firms make essentially every wafer-allocation decision that determines commodity DRAM supply — SK hynix alone held 29.1% of the DRAM market including HBM, 56.4% of HBM, and 18.5% of NAND in Q1 2026 per IDC, as cited in its own prospectus. [5]

Two complications the cannibalisation story must not hide

First: not all HBM capacity is converted DDR5 capacity. SK hynix's M15X is "a next-generation extension fab in Cheongju, Korea that is dedicated primarily to the production of HBM and high-performance DRAM products," and it began wafer input in the first quarter of 2026. [5] Some HBM wafers came from new cleanroom, not from cannibalised commodity lines. A naive cannibalisation story overstates itself by ignoring this.

Second: there is a rare commodity-side capacity addition during the squeeze. Micron reports "Virginia: Initial 1α DDR4 production already launched." [21] Legacy commodity capacity is being added, not only withdrawn.

And a third complication cuts the other way. Advanced packaging is a co-equal bottleneck that a front-end wafer ratio cannot capture at all. "SK hynix, the largest supplier of HBM to Nvidia, has told investors that its advanced packaging lines are at capacity through 2026." [17] Micron "broke ground in January 2025 on an HBM advanced packaging facility" in Singapore to expand capacity "beginning in the first half of calendar 2027." [1] Part of what the market calls the HBM tax is a TSV, hybrid-bonding and packaging constraint that no wafer-per-bit ratio measures.

The supply response is real, enormous, and arrives too late

Every dollar the industry is now committing is a vote against the permanence of the shortage — and every date attached to those dollars lands outside the window where the shortage bites.

Micron is "raising planned U.S. investments to exceed $250 billion through 2035, driven by artificial intelligence-related memory demand," targeting production of 40% of DRAM in the U.S., and poured first concrete at Clay, New York in July 2026, "more than a quarter ahead of schedule." [21] But its own timeline reads: "Idaho facilities: First wafer output expected mid-2027; second fab late 2028," with New York only at first concrete and the "transition from site preparation to vertical construction underway." [21] Not one commodity DRAM bit from that $250 billion arrives inside 2026–2027.

SK hynix commits the counter-argument in writing and then dates it out of relevance: it is "targeting to double our wafer production capacity within the next five years," expects to invest approximately W 600 trillion for the Yongin complex "with target completion of the first cleanroom of the fourth fab by 2033," approximately W 100 trillion for Cheongju and approximately W 400 trillion for a Southwestern complex announced June 29, 2026. [5] Its own chairman, Chey Tae-won, "put the lead time for a greenfield fab at more than five years, placing fresh output near the tail end of the shortage window that he's predicting," and told reporters: "Until 2030, there's still some shortage." [18] Note that Chey reversed himself between March 2026 — no new fab planned, capacity cannot be added on demand — and June 2026. The supply response is being forced by price, exactly as a supply-curve model predicts.

The greenfield counter-argument, in other words, is right in substance and wrong in timing. It is a 2029–2030 answer to a 2026–2027 question.

The offset that actually works on a 2026 clock is not a fab. It is a spreadsheet. Samsung's roughly 80,000 DRAM wafers a month redirected to DDR5 RDIMM [24] — which, against the only global wafer denominator our sources permit us to construct, is on the order of 3.6% of world DRAM wafer supply restored to commodity in a single profit-motivated decision, delivered in a quarter rather than in five-plus years. That denominator, we must stress, is built on the contested Stargate wafer figure and is an order-of-magnitude illustration only; see the callout below.

And the "capex discipline is permanent" premise is already broken

The shortage thesis rests on an assumption that the industry has learned not to build. Watch what actually happened to Micron's guidance over nine months. The FY2025 10-K (October 2025) put capital expenditures at "approximately $4.5 billion in first quarter of 2026," adding that "this level serves as a reasonable quarterly baseline for the planned capital expenditures for 2026" — an annualisation of roughly $18 billion, and the annualisation is ours, not Micron's. [2] By the December 2025 call it was "$20 billion, up from $18 billion previously, to support HBM and 1-gamma DRAM supply capability." [13] By the FQ3-26 10-Q: "We estimate capital expenditures for property, plant, and equipment, net of proceeds from government incentives, to be approximately $27 billion in 2026." [1] That is roughly a 50% escalation in guidance inside three quarters.

And it is real cash, not a press release. "For the first nine months of 2026, net cash used for investing activities consisted primarily of $19.60 billion of expenditures for property, plant, and equipment," against $10.20 billion in the same period of 2025. [1] It is accelerating inside the year, too: capital expenditures net were $7.1 billion in FQ3-26 against $5.0 billion in FQ2-26. [3] [4]

SK hynix's PP&E cash outflows were W 27,519 billion in 2025, W 15,946 billion in 2024 and W 8,325 billion in 2023, and "in 2026, we plan to increase our capital expenditures considerably compared to 2025." [5] (Its chairman separately cited 30.2 trillion won of 2025 spending [18]; that is almost certainly a broader total-investment measure, and we use the prospectus figure and its stated definition rather than blending the two into a trend that does not exist.) More consequentially, SK hynix hard-wires the supply response to the price spike: "We maintain a disciplined capital allocation policy, targeting a capex-to-sales ratio in the mid-30% range based on a rolling three-year average." [5] A fixed capex-to-sales ratio against revenue that has roughly tripled mechanically implies an enormous absolute increase in spending. The higher the price goes, the harder the supply response.

The customers are financing it themselves. Micron's take-or-pay strategic customer agreements have produced "cash deposits and related financial commitments of $22 billion for agreements concluded to date. Approximately $18 billion of these commitments will be in the form of cash deposits." [1] SK hynix's position is identical: "customers have offered to buy SK hynix's EUV scanners and prefund fab lines as available capacity has fallen to near zero." [18] The buyers are pre-funding the very supply that will end the squeeze they are paying for.

1. 2Q25

   HBM3e commands a price premium "more than four times that of DDR5"[9]

   The economics that pulled the wafers into HBM in the first place: a ~4x premium against a ~2.9x wafer penalty is a profitable trade.

2. 2025-10-03

   Micron's FY2025 10-K states the wafer-intensity mechanism — before the spike[2]

   "HBM requires a higher number of wafers and more cleanroom space to produce the same number of bits as conventional DRAM in the same technology node." The mechanism is on the record as a risk before the risk materialises.

3. 2025-10-29

   TrendForce forecasts the inversion[9]

   "Since HBM3e and DDR5 compete for the same production capacity... suppliers may allocate more resources toward server DDR5 to secure earnings." DDR5 profitability projected to surpass HBM3e from 1Q26.

4. 2025-12-08

   Samsung frees around 80,000 DRAM wafers a month back to DDR5 RDIMM[24]

   Reallocating capacity toward DDR5 RDIMM modules "to yield stronger profits." The cannibalisation starts running in reverse. (Teaser only; article body paywalled.)

5. 2025-12-17

   Micron: "the three-to-one trade ratio with DDR5"[13]

   The quantified anchor enters the record — on an earnings call, not in a filing, and never defined.

6. 1Q26

   The trade inverts[6][18]

   "HBM wafer revenue was overtaken by DDR5 64GB RDIMM in 1Q26. This has led HBM profitability to also fall below that of DDR5 64GB RDIMM since 1Q26." Conventional DRAM contract prices had risen roughly 95% in the quarter.

7. 1Q26

   SK hynix's M15X begins wafer input[5]

   A Cheongju extension fab "dedicated primarily to the production of HBM and high-performance DRAM." Some HBM wafers come from NEW cleanroom — not from cannibalised DDR5 lines.

8. 2Q26

   Price growth decelerates to 63% QoQ[18]

   Down from roughly 95% in 1Q26, while HBM's wafer share climbs toward 30%. DDR4 spot rolls over after a ~2,200% run. The most dangerous fact in the file.

9. 2026-06-02

   SK hynix's chairman reverses himself and pledges to double wafer capacity[18]

   Chey Tae-won, three months after saying no new fab was planned: capacity to double in five years, greenfield lead time "more than five years," and "until 2030, there's still some shortage." The supply response is being forced by price.

10. 2026-07-09

    Micron pours first concrete in Clay, New York[21]

    US investment raised above $250 billion through 2035 — and the site is only now transitioning from site preparation to vertical construction.

11. mid-2027

    First wafer output from Micron's Idaho fab[21][13]

    The earliest greenfield capacity date anywhere in the file. Second Idaho fab: late 2028.

12. 2030–2033

    Yongin Fab 1; fourth-fab cleanroom by 2033[5][18]

    SK hynix's W 600 trillion Yongin complex. A 2029–2030 answer to a 2026–2027 question.

The Facts That Would Break This Report — Starting With the One Already Half-Happening

Lead with the fact most dangerous to us.

Prices are decelerating while the cannibalisation intensifies. TrendForce "projected DRAM contract prices to rise 63% in the second quarter after climbing roughly 95% in the first, and DDR4 spot pricing ran up around 2,200% over 12 months before a recent decline." [18] That deceleration is happening precisely while HBM's share of DRAM wafer input marches from 22% toward 30%. [6]

A structural leftward supply shift cannot produce decelerating prices while the shift is intensifying. Either the mechanism was never the marginal price-setter, or demand-side effects — contracted CSP volumes, affordability limits, buyer resistance — now dominate it. We could not verify a 3Q26 contract figure from a source that survives our sourcing gate, so we report the deceleration only as far as the 95%-to-63% step and the DDR4 spot decline, both of which are quotable. This report does not claim the rally is still accelerating. If conventional DRAM contract prices go flat or negative during 2027 — the exact year HBM is forecast to hit 30% of wafer input — the trade ratio is definitively not the price driver, and the central causal claim here is refuted on its own timeline.

The DDR4 detail deserves its own line, because it is awkward for everyone. DDR4 runs on legacy nodes that HBM does not compete for, yet DDR4 spot produced the most violent move in the complex — around 2,200% over 12 months. [18] Pure cannibalisation cannot explain that. Deliberate supply withdrawal through end-of-life decisions is the more likely co-cause, and it means at least part of the "HBM shortage" is an EOL shortage wearing HBM's clothes.

Four more ways this report dies

CXMT. The single largest hole in the thesis is a supplier that none of the twenty-four sources underpinning this report discusses. CXMT is adding conventional-only DRAM capacity — essentially no HBM, ramping DDR5 — at a rate that may exceed the top three's entire annual HBM wafer diversion in wafer terms. If CXMT's conventional additions offset the diversion, the supply-destruction channel is neutralised by a party the hypothesis never mentions. Watch its Shanghai ramp and its share of global conventional DRAM bits. If it crosses roughly 15% of conventional bit supply, the mechanism stops mattering to prices and we would have to retract the causal claim outright. That we cannot source CXMT to a verifiable snapshot in this file is itself a limitation of this report, not a reason to ignore it.

A wafer-start series. Our own arithmetic sets the bar precisely: total DRAM wafer starts must grow above 5.1% in 2026 and 11.4% in 2027 merely to hold conventional wafer starts flat. If a credible series shows growth above those thresholds — plausible, given SK hynix's M15X ramp, Samsung's 1c expansion, and Micron's ID1 first output in mid-2027 — then conventional bits grow even as HBM takes 30% of wafers, and the supply-destruction channel is plugged. We could not find such a series. Its absence is why the wafer-side argument here is labelled asserted.

The ratio improving rather than worsening. Micron insists the trade ratio "only increases with future generations of HBM." [13] TrendForce's own shares do not show that over the forecast window: the implied ratio rises from 2.52x to 2.85x between 2025 and 2026, and is then essentially flat at 2.87x in 2027. Several forces would push it down: HBM4 base dies migrating off DRAM wafers onto logic wafers, denser core dies, and maturing stack yields — SemiAnalysis's observation that today's abnormally low HBM yields are themselves part of the tax cuts directly this way. [15] The single metric to watch is the implied ratio, HBM wafer share divided by HBM bit share. Below roughly 2.5x, the mechanism is decaying and our forward extrapolation inverts.

The quantity-price signature. We have already conceded this one against the original hypothesis, and it cuts against us too if it reverses. Higher quantity at higher price is a demand shock. If a clean plot of industry bit shipments against ASP for 2024–2027 ever shows quantity falling while price rises, the supply-destruction diagnosis is vindicated and ours is wrong.

The steelman, given fairly

None of this makes the shortage soft. TrendForce estimates that "as HBM generations continue evolving in 2027, with larger die sizes and simultaneously rising demand, the crowding-out effect on conventional DRAM capacity is expected to intensify further," with HBM capacity per AI chip rising "from 96GB/192GB to 216GB/288GB" in 2026 and Rubin Ultra reaching "384GB" per GPU in 2027. [6] Micron expects "supply-demand conditions for both DRAM and NAND to remain tight beyond calendar 2027" and believes "that the aggregate industry supply will remain substantially short of the demand for the foreseeable future." [14] [13] TrendForce projects capital expenditures by the world's top eight cloud providers to exceed US$600 billion in 2026, another 40% annual increase. [11]

The forecasters have been serially wrong in one direction, which is itself evidence of something structural. TrendForce "revised its 4Q25 outlook for conventional DRAM pricing upward, from an earlier forecast of 8–13% growth to 18–23%, with a strong likelihood of further upward revision," [9] then revised 1Q26 conventional DRAM contract prices to 90–95% quarter over quarter, up from an earlier estimate of 55–60%, with PC DRAM "projected to increase by over 100% QoQ, setting a new record for a quarterly surge," server DRAM up approximately 90% and mobile DRAM around 90%. [8] TrendForce also estimates global DRAM capacity at 40 exabytes in 2026 with annual growth limited to 10-15% [7] — a figure that flatly contradicts Micron's low-to-mid-20s bit guidance, that we cannot adjudicate, and that, if correct, would make the original hypothesis far stronger than we have credited.

And the human cost is not abstract. A Corsair Vengeance DDR5-6000 32GB kit "cost $134.99 in September before reaching more than $420 in early December," with 64GB kits "attracting prices beyond $500, with one seller listing them for a whopping $881.87 as of December 18." CyberPowerPC "warned in November that contract DRAM prices had jumped 500% since early October." [17]

So the shortage is real, the rationing is real, and the wafer penalty is real. What is not real is the destruction. The trade ratio is physics — 1.85x of it measured, the rest asserted. The allocation is economics. And economics moves on a one-quarter clock: HBM took the wafers when it paid four times DDR5, and Samsung started handing 80,000 of them a month back the moment it did not. [9] [24] The fabs will arrive in 2030. The spreadsheets already did.